1. Field of the Invention
This invention relates to a signal regeneration circuit which is used to regenerate an extremely weak original signal deeply immersed in noise.
2. Description of the Prior Art
A typical conventional signal regeneration circuit of this type has employed a phase-locked loop (referred to as a PLL). This PLL has necessitated the following two requirements, since the PLL should consider for the case that an original signal to be regenerated is likely to be modulated by noise and has more than two types of frequencies so that the original signal is included as a whole wide frequency band.
Firstly, since noise is superposed on the original signal and the original signal including a number of jitters should be processed, the loop band-width of the loop filter should be narrowed to be able to reduce the influence of the noise. Secondly, the pull-in range of the PLL should be sufficiently wide so as to be able to pull in the frequency even if the original signal is transferred from one frequency to other frequencies.
Concerning the first requirement, the reduction in the loop band-width can be solved by increasing the time constant of the loop filter of the PLL. Further, the increase in the pull-in range of the PLL of the second requirement is ordinarily solved by employing an edge trigger type phase frequency comparator (referred to as a PFC) for the phase comparator. Since this PFC can increase the pull-in range up to the lock-in range, the entire PLL can attain sufficiently wide pull-in range even if the loop band-width of the PLL is set to narrow width.
The PFC serves, as shown in (a) to (c) of FIG. 1, to detect the phase difference between two input signals R and S and to produce as an output signal Q having logic level "HIGH" and "LOW" pulses whose width is proportional to the phase difference, and operates to set the output signal Q to "HIGH IMPEDANCE" (the state that is neither logic level "HIGH" nor logic level "LOW") during a period of time in which these two inputs R and S are in phase. For example, when the phase of the input signal R leads, the output signal Q becomes "LOW" at the rise of the input signal R, and the output signal Q becomes "HIGH IMPEDANCE" at the rise of the input signal S. When the phase of the input signal R, on the other hand, lags, the output Q becomes "HIGH" at the rise of the input signal S, and the output signal Q becomes "HIGH IMPEDANCE" at the rise of the input signal R.
Accordingly, if the input signal to the PFC lacks one or more pulses or includes excessive pulse or pulses, the PFC might invert the output signal Q immediately after the pulse irregularity of the input signal. In other words, if the input signal R lacks, as shown in (a) of FIG. 2, a pulse P.sub.1, the PFC operates in the same manner as the phase of the input signal R lags with respect to the phase of the input signal S (refer to (b) of FIG. 2), and as a result the output signal Q unfavorably becomes "HIGH" instead of becoming "LOW" (refer to (c) of FIG. 2). The output signal Q thus varied is applied to a voltage controlled oscillator (referred to as a VCO) through a loop filter. Since the VCO judges such an abrupt change in the output signal Q as a rapid change in the control voltage, the VCO regards the entire loop of the PLL as in a lock-out state, and operates to correct to hold in range.
If the input signal R includes an excessive pulse P.sub.2 as shown in (a) of FIG. 3, the PFC operates in the same manner as the phase of the input signal R leads with respect to the phase of the input signal S (refer to (b) of FIG. 3), and as a result the output signal Q unfavorably becomes "LOW" instead of becoming "HIGH" (refer to (c) of FIG. 3). In this case, the VCO judges such an output signal Q thus varied abruptly as a rapid change in the control voltage, and accordingly regards the entire loop of the PLL as in a lock-out state, and operates to correct to hold in range.
The signal which lacks one or more pulses or includes an excessive pulse or pulses due to a chattering, etc. as described above can be frequently observed in a signal deeply immersed in an ordinary noise. However, if such a signal is inputted to a PLL, the PLL should frequently correct to hold in range as described above. As a result, the PLL cannot maintain the lock-in range in operation.